1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the invention relates to a very fine semiconductor device with a transistor having a channel region in which impurities are implanted. In addition, the invention relates to a structure of a row core circuit in a NAND type flash memory.
2. Description of the Related Art
Recently, EEPROMs (Electrically Erasable Programmable Read Only Memory) have been known as non-volatile semiconductor memories capable of electrically writing and erasing data. EEPROMs include a flash memory capable of effecting electrical batch-erase. In particular, NAND type flash memories, which permit easy realization of higher integration, are widely used.
Manufacturing methods of conventional NAND type flash memories are proposed, for instance, in S. Aritome, et al., IEDM (1994) pp. 61–64, “A 0.67 μm2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI CELL) FOR 3V-only 256 Mbit NAND EEPROMs”; or Y. Takeuchi, et al., 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 102–103, “A Self-Aligned STI Process Integration for Low Cost and Highly Reliable 1 Gbit Flash Memories.” According to these proposals, an element isolation region between memory cells is formed by STI (Shallow Trench Isolation) technology. A floating gate is formed so as to have a self-aligned structure (SA-STI) relative to the element isolation region. Thereby, a memory cell array comprising fine memory cells arranged with high density is realized. In the manufacturing process, the element isolation region is formed after a gate oxide film and a part or all of a floating gate electrode material have been formed. In addition, impurities are introduced by ion implantation into channel regions of transistors used for memory cells and a peripheral control system, before the gate oxide film is formed. Thereafter, the gate insulating film is formed. Thermal diffusion of the introduced impurities is effected by heat treatment in a subsequent step of forming the element isolation region. The impurities are activated by the thermal diffusion.
In the NAND type flash memory, when data “1” is written in the memory cell (i.e. a threshold voltage for data erase state is kept without introducing electrons in the floating gate), the bit line is charged with initial potential. In addition, a write voltage is applied to the selected word line, and a transfer voltage is applied to the unselected word line. The potential of the channel region of the memory cell transistor is raised by capacitive coupling, thereby preventing injection of electrons in the floating gate. If the impurity concentration of the channel region is lowered, the channel capacitance decreases and the channel region potential tends to rise easily. As a result, the characteristics of write of data “1” in the memory cell are enhanced.
Several methods of fabricating flash memories have been proposed, considering the above write operation and paying attention to the control of impurity concentrations in channel regions of memory cell transistors. For example, Jpn. Pat. Appln. KOKAI Publication No. 2002-009173 discloses a method wherein a gate oxide film and an element isolation region are successively formed, following which ion implantation is effected through the gate oxide film and a floating gate. According to this method, the impurity concentration profile in the channel region is not affected by heat treatment in an element isolation region forming step. Accordingly, a steep profile of impurity concentration can be realized. Thus, even if the channel length is decreased, the impurity concentration in the channel region can be sufficiently controlled.
U.S. patent application Ser. No. 10/058,343 (corresponding to Japanese Patent Application No. 2001-23973) presents a proposal relating mainly to a NAND type flash memory. Specifically, it discloses a method wherein after a mask is formed on a memory cell transistor, impurities are obliquely ion-implanted in an impurity diffusion layer between adjacent select transistors. According to this method, the impurity concentration in the channel region of the memory cell transistor is made equal to that in the channel region of the select transistor, and the characteristics of the select transistor can easily be controlled.
U.S. patent application Ser. No. 09/956,986 (corresponding to Japanese Patent Application No. 2000-291910) also presents a proposal relating to a NAND type flash memory. Specifically, it discloses a method of removing an inter-gate insulating film that isolates a floating gate and a control gate in gate electrodes of a peripheral control system transistor and a select transistor. Thereby, the floating gate and control gate can be electrically connected.
Jpn. Pat. Appln. KOKAI Publication No. 59-74677 discloses, as shown in FIGS. 4–11, that an opening portion is made in an insulating film between a floating gate and a control gate in a peripheral transistor. This increases the degree of freedom in designing wiring.
As has been described above, various proposals have been presented with respect to methods of manufacturing flash memories. However, in the case of the method of forming an element isolation region after the formation of a channel region, impurities in the channel region tend to easily diffuse, and miniaturization of the channel length of the transistor becomes difficult. The reason is that many thermal steps exist after the formation of the channel region. This problem is conspicuous, in particular, when the gate length of the memory cell transistor is less than about 0.2 μm.
On the other hand, as the degree of miniaturization progresses, it becomes difficult to carry out the method wherein the ion implantation in the channel region of the memory cell transistor and the ion implantation in the channel region of the select transistor are performed in different steps. Moreover, since the number of lithographic steps increases, the total number of fabrication steps increases. This method is hardly feasible, for example, when a very fine, high-density memory cell unit is to be formed, which would have a channel length of about 0.3 μm or less of the select transistor and a channel length of about 0.15 μm or less of the memory cell transistor.
However, if the impurity region in the channel region of the memory cell transistor and the impurity region in the channel region of the select transistor are to be formed at the same time, it is difficult to increase the impurity concentration in the channel region of the select transistor. As a result, the cut-off characteristics of the select transistor may deteriorate. In other words, there is no choice but to set the impurity concentration in the channel region of the select transistor at a concentration value that satisfies memory cell characteristics necessary for the memory cell transistor. This concentration value is usually lower than the concentration necessary for the select transistor. In short, there is no choice but to set the impurity concentration in the channel region of the select transistor at a concentration value lower than an ideal value. Consequently, the select transistor may not normally operate because the threshold voltage decreases and an off-leak current increases. The memory cell characteristics in this context refer to data retention characteristics, write/erase characteristics and the degree of degradation in characteristics due to write/erase.
In the NAND type flash EEPROM, like other semiconductor devices such as DRAMs (Dynamic Random Access Memories) or SRAMs (Static RAMs), one word line is selected by a row decoder, and data write/read is effected for a selected memory cell (page). The row decoder comprises a row main decoder circuit and a row core circuit (row sub-decoder circuit). In accordance with row address signals, the row main decoder circuit generates predetermined voltages to be applied to control gate lines and select gate lines in the memory cell array. The row core circuit functions as a switch between the row main decoder circuit and the memory cell array.
The structure of the row core circuit will now be described with reference to FIGS. 1A and 1B. FIG. 1A is a plan view of the row core circuit, and FIG. 1B is a cross-sectional view taken along line 1B—1B in FIG. 1A.
As is shown in the Figures, a plurality of active areas AA (Active Area) are provided in matrix on a silicon substrate 200. Element isolation regions STI are provided between adjacent active areas AA. Transfer gate transistors TGTD, TGTS, TGT, TGT, . . . , are formed on the electrically isolated active regions AA. Each of the transfer gate transistors TGTD, TGTS, TGT, TGT, . . . , has a gate electrode TG and impurity diffusion layers (not shown). The gate electrode TG is provided on a gate insulating film 210 on the active area AA. The gate electrode TG comprises a polysilicon film 220 and a polysilicon film 240 provided over the polysilicon film 220 via an inter-gate insulating film 230. The polysilicon films 220 and 240 are electrically connected on the active area AA. Interlayer insulating films 260 and 280 are provided so as to cover the transfer gate transistors TGTD, TGTS and TGT.
Gate electrodes TG of transfer gate transistors TGTD, TGTS and TGT provided in the active areas AA of the same row are commonly connected. Impurity diffusion layers (drain regions) on one side of the transfer gate transistors TGTD, TGTS and TGT are connected to a drain-side select gate line SGD, a source-side select gate line SGS and control gate lines CG, respectively. More specifically, the select gate lines SGD and SGS and control gate lines CG are led into the row core circuit by shunt wiring 290 provided in the interlayer insulating film 260, and connected to the impurity diffusion layers of the associated transfer gate transistors TGTD, TGTS and TGT via contact holes C20. Impurity diffusion layers (source regions) on the other side of the transfer gate transistors TGTD, TGTS and TGT are supplied with predetermined voltages from the row main decoder via metal wiring layers 300.
FIG. 1C is an enlarged view of FIG. 1B. As is shown in FIG. 1C, a parasitic MOS transistor exists in a region between adjacent active areas AA arranged along the control gate line. The parasitic MOS transistor is formed, with the polysilicon film 240 serving as a gate electrode thereof, and the gate insulating film 230 and element isolation region STI as a gate insulating film thereof. A high voltage Vpgm is applied to the gate electrodes TG to turn on the transfer gate transistors TGTD, TGTS and TGT. At this time, the parasitic MOS transistor may be turned on. In such a case, an inversion region CH forms in the vicinity of the element isolation region STI. Consequently, adjacent active areas AA arranged with the element isolation region STI interposed may be rendered conductive.
The transfer gate transistors TGT are designed such that a turned-on transfer gate transistor TGT and a turned-off transfer gate transistor TGT may not be arranged adjacent to each other in the same row. In other words, the control gate lines connected to the transfer gate transistors TGT provided in the same row are designed such that adjacent control gate lines are not set in the selected state and unselected state. The reason is as follows. At the time of data write, in particular, a high voltage Vpgm is applied to the active area AA (impurity diffusion layer) of the selected transfer gate transistor TGT. On the other hand, 0V is applied to the active area AA of the unselected transfer gate transistor TGT. If the potential difference increases between the adjacent active areas AA, insulation therebetween cannot be maintained.
However, in the case where the transfer gate transistors TGTD and TGTS connected to the select gate lines SGD and SGS and the transfer gate transistors TGT connected to the control gate lines CG are provided in the same row, it is difficult to avoid such a situation from occurring, that both transistors have the relationship of selection and non-selection.
This situation will be described with reference to FIG. 1C. As shown in FIG. 1C, the transfer gate transistor TGT connected to the selected control gate line CG and the transfer gate transistor TGTD connected to the unselected select gate line SGD are arranged adjacent to each other in the same row. In this case, both active areas AA have a high potential Vpgm and a ground potential GND, with the element isolation region STI interposed. In addition, the polysilicon film 240, which becomes part of the gate electrode TG, is present on the element isolation region STI. The polysilicon film 240 is supplied with the high voltage Vpgm to turn on the transfer gate transistors TGTD and TGT. In this case, a potential difference between both active areas AA exceeds the withstand voltage of the element isolation region STI. As a result, the element isolation region STI may not maintain electrical insulation between the active areas AA.
The problem with the element isolation may be solved by increasing the width d10 (see FIG. 1A) of the element isolation region STI in the direction of the control gate line CG. However, there are locations at random, where the transfer gate transistors TGT and the transfer gate transistors TGTD and TGTS are arranged adjacent to each other in the direction of control gate lines. In order to solve the problem, it is thus necessary to increase the width d10 of element isolation regions over the entire area of the row core circuit. If this is done, the area of the row core circuit increases and the NAND type flash EEPROM cannot be reduced in size.